Clock doubler with delay line

Inverter 256, the output of which is connected to the gate electrode of transistor 254. the clock signal CLKBP is also apphed to the input of another inverter 260, the output of which is connected to the gate electrode of an n-channel transistor 262. the drain of transistor 262 is connected to central node 230. the source of transistor 262 is selectively coupled to VSS via either of n-channel transistors 264 or 266. the gate electrode of transistor 264 is connected to the delayed clock signal CLKDLYB from the clock control circuit 16. a NOR gate 268 receives the high timing signal HTIME at one input and receives the clock timing modification signal CLKTMB via line 222 at a second input. the output of gate 268 is connected to the gate electrode of transistor 266. clock selector circuitry 18 depends on the status of the signal CLKTMB, which is the control signal programmed by the mode registers. CLKTMB the control signal programmed by the mode registers. the timing signal HTIME arrives and causes the signal DCLKB to be generated. DCLKB will also go high and it will stay high for however long the HTIME one-shot lasts. Consequently, this part of the signal DLCLKB is essentially the same as the HTIME signal. the low timing signal LTTME for which, unlike HTIME, the time delay is not programmed by the signal CLl, provides a fixed one-shot delay. the HTIME signal In the clock doubler mode, the HTIME signal provides a high pulse and then goes low, and then the LTIME signal provides a further pulse. If the clock doubler mode is not active, then the HTIME signal simply provides the high pulse and times out. the riming signal CLKTMB For the clock doubler mode, the riming signal CLKTMB must be on (low level) and CLl must be off (low level) in order for L ⁇ ME to provide another high pulse during the same external clock cycle. the HTTME signal In the normal mode of operation, the HTTME signal will determine the high time of the output signal DCLKB, and it will time out without anything else happening. the signal output is desired to be very fast because a signal was intercepted from the input buffer. It is modified and put back into the input buffer circuit as DCLKB, and the circuitry is desired to result in minimum skews. It takes time to generate the signals HTTME and LTTME. If the circuit relied simply on HTIME, it would not provide a signal fast enough and would result in additional skew and delay. this embodiment uses a feed forward approach so that when the clock fires (CLKBP changes states), it immediately (or very

Connected to the gate electrode of a p-channel transistor 246. A further transistor 248 is connected in series with transistor 246 so that the source-drain paths thereof selectively connect node 230 to VCC. The gate electrode of p-channel transistor 248 is connected to the output of an inverter 250. Inverter 250 inverts the inverted clock signal CLKBP from the clock buffer circuit 14. A fifth path to a power supply voltage (VSS) is provided. The inverted clock timing signal CLKBP is apphed to the gate electrode of an n-channel transistor 252 which is connected in series with another n-channel transistor 254. The source-drain paths of transistor 252, 254 selectively connect node 230 to VSS. The low timing signal LTIME from the clock one-shot circuits 20 is inverted by an inverter 256, the output of which is connected to the gate electrode of transistor 254. Sixth and seventh paths from node 230 to a power supply are provided. The clock signal CLKBP is also apphed to the input of another inverter 260, the output of which is connected to the gate electrode of an n-channel transistor 262. The drain of transistor 262 is connected to central node 230. The source of transistor 262 is selectively coupled to VSS via either of n-channel transistors 264 or 266. The gate electrode of transistor 264 is connected to the delayed clock signal CLKDLYB from the clock control circuit 16. A NOR gate 268 receives the high timing signal HTIME at one input and receives the clock timing modification signal CLKTMB via line 222 at a second input. The output of gate 268 is connected to the gate electrode of transistor 266. It will be appreciated that the operation of clock selector circuitry 18 depends on the status of the signal CLKTMB, which is the control signal programmed by the mode registers. In general, the timing signal HTIME arrives and causes the signal DCLKB to be generated. When HTIME goes high, DCLKB will also go high and it will stay high for however long the HTIME one-shot lasts. Consequently, this part of the signal DLCLKB is essentially the same as the HTIME signal. When the clock signal goes in the other direction, however, the low timing signal LTTME, for which, unlike HTIME, the time delay is not programmed by the signal CLl, provides a fixed one-shot delay. In the clock doubler mode, the HTIME signal provides a high pulse and then goes low, and then the LTIME signal provides a further pulse. If the clock doubler mode is not active, then the HTIME signal simply provides the high pulse and times out. For the clock doubler mode, the riming signal CLKTMB must be on (low

Which is connected to the drain of n-channel transistor 288, the source of which is connected to ground. Transistor 286 has a gate electrode connected to the output of inverter 284 (the HTIME signal), and transistor 288 ⁇ has a gate electrode coupled to receive the' high time enabling signal HTEN. Circuitry for providing the low timing signal LTTME is very similar and includes a constant current source formed around transistors 290-295. the output of that constant current source appears on a conductive line 291 which is connected to one side of transistors functioning as capacitors 296, the other sides of which are connected to VSS. Conductive line 291 is applied to the input of an inverter 297, and line 291 is connected selectively to ground via the source-drain paths of series-connected transistors 298 and 299. the output of inverter 297 provides the low timing signal LTIME, which is also connected to the gate electrode of transistor 298. the gate electrode of transistor 299 is connected to receive the low timing enabling signal LTEN. the first constant current source of circuit 20 includes transistor 272 which turns on and off under control of the mode register signal CLl. When transistor 272 is conductive, it reduces the resistance between transistors the low time enable signal LTEN is kept high when the circuitry is not in the clock doubler test mode. With LTEN high, transistor 290 is kept off. Accordingly, the low riming signal LTTME, which is provided to the clock selector circuitry, is used only when the clock doubler mode is enabled. the invention addresses the problem of duty cycles different than 50% in the external clock signal by modifying the internal clock high time, using a precision delay time which is triggered by the rising edge of the external clock. Furthermore, the high pulse generated, under "normal operation" (non-doubler mode), modifies the pulse width differently for different /CAS latencies (our implementation programs the same pulse duration for /CAS latencies of 2 and 3, but changes the pulse duration for /CAS latency of 1. the invention includes programming different internal pulse widths for all possible /CAS latencies. If the mode register signal CLl is high, then the voltage at the gate electrode of transistor 272 will be low, and that transistor will be nonconductive. HTIME is shorter in duration. the generation of the other timing signal LTTME is similar, but it is not modified on the basis of the status of the CLl signal. However, in a variation of the preferred embodiment, a similar change in the current can be achieved by adding a transistor and/or further resistances between transistors 292 and 295. Fig. 7 shows the circuitry leading to the

Is limited when the external clock signal has a duty cycle other than 50%, i.e. when the external clock signal is in the high state for a high percentage of the clock cycle time or when the external clock signal is in the high state for a low percentage of the clock cycle time. Disclosure of Invention To overcome the aforementioned problems, a technique is used where an internal clock or timer provides a clock or timing signal so that the minimum internal requirement for the internal clock high time is satisfied. This minimum time permits acceptable internal clock low durations with all expected external clock frequencies. However to ensure that optimal internal clock timing exists for all anticipated frequencies, the timing is preferably programmable. In a preferred form, the "CAS latency" is user programmable to alter the internal pulse width. Preferably, the internal timing circuit includes at least one, and preferably two, timers, e.g. one-shot circuits. Moreover, a clock doubler circuit is incorporated as part of the circuit and method. This clock doubler allows the external clock signal to run at Vz the rate of the on-chip clock circuits. Preferably the clock doubler will allow instruction commands to be accepted on each external clock edge, but circuit modifications would allow external commands to be accepted on only one edge of the external clock, while internal functionality and input/output data would "burst" at double the external clock rate. The internally controlled clock high time eliminates the performance problems associated with the high duty cycles of some external clock signals. The clock doubler reduces the test times and allows testing at the highest rated clock speeds of a device on low speed and low cost production testers. Moreover, while the clock doubler is to be used primarily in a test mode, it can provide system designers with the ability to clock commands and data on each transition of the external clock. As noted, the clock high time is a function of /CAS latency which allows internal circuit optimization for supported /CAS latencies. The external clock signal should be reasonably symmetrical when using the clock doubler mode in order to generate a stable double rate clock signal internally. However, when in normal mode, the programmable clock modification circuitry compensates for large variations in duty cycle. In one embodiment, a one-shot is used with a look-ahead technique (a feed forward technique) which employs the leading edge of the external clock signal, uses the external clock signal, adds a time delay, and turns off the original external clock signal (internally) so that the trailing edge of the internally generated clock signal is governed by the internal circuitry. This approach generates one-shot pulses for normal