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Part 1 of this series described how digital signals propagate through PC boards [Refs. 1, 2, 5, 6]. In part 2, we look at specific board designs to achieve low EMI. The biggest issue I see in my clients’ board designs is poor layer stack-up.Reiterating the two fundamental rules from part 1 and realizing digital signals and power (transients) are electromagnetic waves moving in the dielectric layer, we see there are two very important principles when it comes to PC board design:Every signal and power trace (or plane) on a PC board should be considered a transmission line.Digital signal propagation in transmission lines is really the movement of electromagnetic fields in the space between the copper trace and GRP.To construct a transmission line, you need two adjacent pieces of metal that capture or contain the field. For example, a microstrip over an adjacent ground return plane (GRP) or a stripline adjacent to a GRP or a power trace (or plane) adjacent to a GRP. For example, locating multiple signal layers between power and ground reference planes will lead to real EMI issues for fast signals. Observing these two rules will dictate the layer stack-up. In other words, every signal or power trace (routed power) must have an adjacent GRP and all power planes should have an adjacent GRP. Multiple GRPs should be tied together with a matrix of stitching vias. In this article, we’ll examine several stack-up designs. 03.11.2025 03.06.2025 03.05.2025 Typical six-layer design (Altium) One stack-up I frequently see is this six-layer design (Figure 1). This probably worked well enough in the 1990s through early 2000s, but with today’s much faster and mixed signal technologies, it’s recipe for EMI disaster. There are two issues with this: the bottom two signal layers are referenced to the power plane and the power and ground return planes are non-adjacent and too far apart. Figure 1 A very common, but poor, EMI stack-up design (6-layer example). Signal layers 4 and 6 are referenced to power, while the GRP and power planes are non-adjacent with two signal layers in between. This will couple power transients on those two signal layers.With few exceptions (some DDR RAM power and signals, for example) currents want to return to their sources, which are referenced to the GRP. Referencing these signals to the power plane is very EMI-risky, because there is no clearly defined return path, except through plane-to-plane capacitance, which in this case is relatively small. In addition, these gaps in the return path result in field leakage into other areas of the board’s dielectric layers. That, in turn, leads to cross-coupling and radiated EMI.The second issue occurs when we have the power and GRP separated by two signal layers. Any power network transients will cross-couple within the dielectric layers, coupling to any signal traces on layers 3 and 4 along the way. You also lose any plane-to-plane capacitance benefit if these planes are separated by more than 3-4 mils.The following are a several ideas for PC board

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What goes around comes aroundDo you believe in karma? There are some that say whatever you believe is effectively true as it will determine your actions. That may be true; however, there are some realities that are independent of whether anyone believes in them or not. Actions having reactions is one of these. Or if you like, what goes around comes around.An inescapable reality of PCB design is that your signals must have a return path for your circuits to function. This is true for all signals, analog, digital and power. For simple, less complex circuits; such as single and double-layer boards, traces are sufficient to provide the necessary return paths. However, for smaller boards with more complex routing, multilayer PCBs with vias is required. For multilayer boards, it is essential that good stackup layer tips are employed, which includes determining the best usage for signal, ground and power planes. Dedicating a layer(s) to power is less common than signal and ground power planes and poses some unique challenges. Let’s explore these by determining the best techniques for a 4 layer power plane design. 4 Layer PCB Stackup Design A multilayer PCB is defined as having “3 or more” conductive layers, where each internal layer may be for signals, ground or power. Although, it is possible to design a 3 layer board with a power plane, practically, a 4 layer PCB, shown in the figure below, is most likely the smallest stackup that will contain a power layer. 4 layer PCB structureAs shown in the figure above, a 4 layer stackup includes two internal layers. This means that your board will include blind vias. Most often, one of these will be a signal layer and the other a ground plane. However, both internal layers may be ground planes, as there are EMI advantages to having parallel ground layers. Another stackup alternative is to have a power plane and a ground plane; however, it is highly inadvisable to have two internal signal layers adjacent to each other. There are also situations where multiple power planes may be needed, but there are significant challenges to be considered for these designs, as discussed below.4 Layer PCB Power Plane Design ChallengesWhen designing multilayer boards of any number of layers there are some stackup tips that should be followed to ensure the operation and help facilitate your board’s manufacturing. These include; configuring your stackup symmetrically and minimizing the distance between ground and power planes. Adhering to these and other multilayer stackup design guidelines pose challenges for 4 layer power plane designs, as listed below.Design Challenges: Multiple power planes For high functionality PCBs, it is not uncommon for components to have different voltage level requirements for

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Stack-ups that comply with the transmission line aspects of digital signal propagation.Four-layer board: Design 1 A good four-layer board stack-up for improved EMI (Figure 2). Instead of a power plane, we use either routed or poured power, along with signals on layers 2 and 3. Thus, each signal/power trace is adjacent to a GRP. Also, it’s easy to run vias between all layers, so long as the two GRPs are connected together with a matrix of stitching vias. If you run a row of stitching vias along the perimeter (say, every 5mm) you form a Faraday cage. Figure 2 This good four-layer board stack-up for improved EMI keeps the signals and routed power near the ground reference planes.Four-layer board: Design 2 If, on the other hand, you’d prefer to have access to the signal and routed/poured power traces, you may simply reverse the layer pairs, such that the two GRP layers are in the middle and the two signal layers are positioned at the top and bottom, with routed power and sufficient decoupling caps, rather than a power plane (Figure 3). Figure 3 This good four-layer board stack-up for improved EMI places the ground reference planes inside the board.For both four-layer designs, you want to run a pattern of stitching vias connecting the two GRPs about 1cm apart, maximum.Eight-layer board (Altium) Both the four- and eight-layer board designs (Figure 4) follow the two fundamental rules that preserve good transmission line design. In addition, for the eight-layer design, the power and GRP planes are now 4 mils apart, providing fairly good plane-to-plane capacitance. Closer would even be better. For example, a spacing of 1 mil to 3 mils is ideal for minimizing EMI. All GRPs should be stitched together with a 1 cm pattern of vias. Figure 4 A good EMI stack-up design (8-layer example). All signal layers are referenced to an adjacent GRP, while power is also referenced to an adjacent GRP.Of course, there are many more iterations on creating proper transmission line pairs between signal and GRP or power and GRP.What about two-layer boards? Simple, just run signals and routed power on layer 1 and use a GRP on layer 2. Well, that may have worked in yesterday’s technology. in today’s technology, we often need to use at least two layers to run signals. The answer is to run “triplets” with a ground return trace between two signal traces (Figure 5). This was an idea from Daniel Beeker, Senior Applications Engineer with NXP Semiconductor [Ref 5]. Figure 5 An example of routed triplets for signals, as well as attempting to preserve the transmission line principles for routed power. Courtesy: Daniel Beeker, NXP SemiconductorHere, we see an attempt to preserve the transmission line properties for the routed power. The example also shows analog signal traces with a ground return trace between them—a routed “triplet.” Because the electromagnetic field is captured adequately between each signal trace and the return trace, there is little field leakage.If you’d like to learn much more

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